/* ###*B*###
 * Erika Enterprise, version 3
 * 
 * Copyright (C) 2017 - 2018 Evidence s.r.l.
 * 
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 * 
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
 * General Public License, version 2, for more details.
 * 
 * You should have received a copy of the GNU General Public License,
 * version 2, along with this program; if not, see
 * < www.gnu.org/licenses/old-licenses/gpl-2.0.html >.
 * 
 * This program is distributed to you subject to the following
 * clarifications and special exceptions to the GNU General Public
 * License, version 2.
 * 
 * THIRD PARTIES' MATERIALS
 * 
 * Certain materials included in this library are provided by third
 * parties under licenses other than the GNU General Public License. You
 * may only use, copy, link to, modify and redistribute this library
 * following the terms of license indicated below for third parties'
 * materials.
 * 
 * In case you make modified versions of this library which still include
 * said third parties' materials, you are obligated to grant this special
 * exception.
 * 
 * The complete list of Third party materials allowed with ERIKA
 * Enterprise version 3, together with the terms and conditions of each
 * license, is present in the file THIRDPARTY.TXT in the root of the
 * project.
 * ###*E*### */

/** @file	ee_nvic.h
 *  @brief	ARM Cortex-M Nested Vector Interrupt Controller (NVIC) Macros
 *  @author	Giuseppe Serano
 *  @date	2018
 */ 

#ifndef	OSEE_CORTEX_M_NVIC_H
#define	OSEE_CORTEX_M_NVIC_H

#include "ee_platform_types.h"
#include "ee_mcu_common_types.h"

#if (defined(__cplusplus))
extern "C" {
#endif

/* NVIC registers (NVIC) */
#define	OSEE_CORTEX_M_NVIC_INT_TYPE_R		OSEE_HWREG(0xE000E004U)
#define	OSEE_CORTEX_M_NVIC_ACTLR_R		OSEE_HWREG(0xE000E008U)
#define	OSEE_CORTEX_M_NVIC_VTOR				OSEE_HWREG(0xE000ED08U)

#define	OSEE_CORTEX_M_NVIC_EN0_R		OSEE_HWREG(0xE000E100U)
#define	OSEE_CORTEX_M_NVIC_EN1_R		OSEE_HWREG(0xE000E104U)
#define	OSEE_CORTEX_M_NVIC_EN2_R		OSEE_HWREG(0xE000E108U)
#define	OSEE_CORTEX_M_NVIC_EN3_R		OSEE_HWREG(0xE000E10CU)
#define	OSEE_CORTEX_M_NVIC_EN4_R		OSEE_HWREG(0xE000E110U)
#define	OSEE_CORTEX_M_NVIC_DIS0_R		OSEE_HWREG(0xE000E180U)
#define	OSEE_CORTEX_M_NVIC_DIS1_R		OSEE_HWREG(0xE000E184U)
#define	OSEE_CORTEX_M_NVIC_DIS2_R		OSEE_HWREG(0xE000E188U)
#define	OSEE_CORTEX_M_NVIC_DIS3_R		OSEE_HWREG(0xE000E18CU)
#define	OSEE_CORTEX_M_NVIC_DIS4_R		OSEE_HWREG(0xE000E190U)
#define	OSEE_CORTEX_M_NVIC_PEND0_R		OSEE_HWREG(0xE000E200U)
#define	OSEE_CORTEX_M_NVIC_PEND1_R		OSEE_HWREG(0xE000E204U)
#define	OSEE_CORTEX_M_NVIC_PEND2_R		OSEE_HWREG(0xE000E208U)
#define	OSEE_CORTEX_M_NVIC_PEND3_R		OSEE_HWREG(0xE000E20CU)
#define	OSEE_CORTEX_M_NVIC_PEND4_R		OSEE_HWREG(0xE000E210U)
#define	OSEE_CORTEX_M_NVIC_UNPEND0_R		OSEE_HWREG(0xE000E280U)
#define	OSEE_CORTEX_M_NVIC_UNPEND1_R		OSEE_HWREG(0xE000E284U)
#define	OSEE_CORTEX_M_NVIC_UNPEND2_R		OSEE_HWREG(0xE000E288U)
#define	OSEE_CORTEX_M_NVIC_UNPEND3_R		OSEE_HWREG(0xE000E28CU)
#define	OSEE_CORTEX_M_NVIC_UNPEND4_R		OSEE_HWREG(0xE000E290U)
#define	OSEE_CORTEX_M_NVIC_ACTIVE0_R		OSEE_HWREG(0xE000E300U)
#define	OSEE_CORTEX_M_NVIC_ACTIVE1_R		OSEE_HWREG(0xE000E304U)
#define	OSEE_CORTEX_M_NVIC_ACTIVE2_R		OSEE_HWREG(0xE000E308U)
#define	OSEE_CORTEX_M_NVIC_ACTIVE3_R		OSEE_HWREG(0xE000E30CU)
#define	OSEE_CORTEX_M_NVIC_ACTIVE4_R		OSEE_HWREG(0xE000E310U)
#define	OSEE_CORTEX_M_NVIC_PRI0_R		OSEE_HWREG(0xE000E400U)
#define	OSEE_CORTEX_M_NVIC_PRI1_R		OSEE_HWREG(0xE000E404U)
#define	OSEE_CORTEX_M_NVIC_PRI2_R		OSEE_HWREG(0xE000E408U)
#define	OSEE_CORTEX_M_NVIC_PRI3_R		OSEE_HWREG(0xE000E40CU)
#define	OSEE_CORTEX_M_NVIC_PRI4_R		OSEE_HWREG(0xE000E410U)
#define	OSEE_CORTEX_M_NVIC_PRI5_R		OSEE_HWREG(0xE000E414U)
#define	OSEE_CORTEX_M_NVIC_PRI6_R		OSEE_HWREG(0xE000E418U)
#define	OSEE_CORTEX_M_NVIC_PRI7_R		OSEE_HWREG(0xE000E41CU)
#define	OSEE_CORTEX_M_NVIC_PRI8_R		OSEE_HWREG(0xE000E420U)
#define	OSEE_CORTEX_M_NVIC_PRI9_R		OSEE_HWREG(0xE000E424U)
#define	OSEE_CORTEX_M_NVIC_PRI10_R		OSEE_HWREG(0xE000E428U)
#define	OSEE_CORTEX_M_NVIC_PRI11_R		OSEE_HWREG(0xE000E42CU)
#define	OSEE_CORTEX_M_NVIC_PRI12_R		OSEE_HWREG(0xE000E430U)
#define	OSEE_CORTEX_M_NVIC_PRI13_R		OSEE_HWREG(0xE000E434U)
#define	OSEE_CORTEX_M_NVIC_PRI14_R		OSEE_HWREG(0xE000E438U)
#define	OSEE_CORTEX_M_NVIC_PRI15_R		OSEE_HWREG(0xE000E43CU)
#define	OSEE_CORTEX_M_NVIC_PRI16_R		OSEE_HWREG(0xE000E440U)
#define	OSEE_CORTEX_M_NVIC_PRI17_R		OSEE_HWREG(0xE000E444U)
#define	OSEE_CORTEX_M_NVIC_PRI18_R		OSEE_HWREG(0xE000E448U)
#define	OSEE_CORTEX_M_NVIC_PRI19_R		OSEE_HWREG(0xE000E44CU)
#define	OSEE_CORTEX_M_NVIC_PRI20_R		OSEE_HWREG(0xE000E450U)
#define	OSEE_CORTEX_M_NVIC_PRI21_R		OSEE_HWREG(0xE000E454U)
#define	OSEE_CORTEX_M_NVIC_PRI22_R		OSEE_HWREG(0xE000E458U)
#define	OSEE_CORTEX_M_NVIC_PRI23_R		OSEE_HWREG(0xE000E45CU)
#define	OSEE_CORTEX_M_NVIC_PRI24_R		OSEE_HWREG(0xE000E460U)
#define	OSEE_CORTEX_M_NVIC_PRI25_R		OSEE_HWREG(0xE000E464U)
#define	OSEE_CORTEX_M_NVIC_PRI26_R		OSEE_HWREG(0xE000E468U)
#define	OSEE_CORTEX_M_NVIC_PRI27_R		OSEE_HWREG(0xE000E46CU)
#define	OSEE_CORTEX_M_NVIC_PRI28_R		OSEE_HWREG(0xE000E470U)
#define	OSEE_CORTEX_M_NVIC_PRI29_R		OSEE_HWREG(0xE000E474U)
#define	OSEE_CORTEX_M_NVIC_PRI30_R		OSEE_HWREG(0xE000E478U)
#define	OSEE_CORTEX_M_NVIC_PRI31_R		OSEE_HWREG(0xE000E47CU)
#define	OSEE_CORTEX_M_NVIC_PRI32_R		OSEE_HWREG(0xE000E480U)

#define	OSEE_CORTEX_M_NVIC_CPUID_R		OSEE_HWREG(0xE000ED00U)
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_R		OSEE_HWREG(0xE000ED04U)
#define	OSEE_CORTEX_M_NVIC_VTABLE_R		OSEE_HWREG(0xE000ED08U)
#define	OSEE_CORTEX_M_NVIC_APINT_R		OSEE_HWREG(0xE000ED0CU)
#define	OSEE_CORTEX_M_NVIC_SYS_CTRL_R		OSEE_HWREG(0xE000ED10U)
#define	OSEE_CORTEX_M_NVIC_CFG_CTRL_R		OSEE_HWREG(0xE000ED14U)
#define	OSEE_CORTEX_M_NVIC_SYS_PRI1_R		OSEE_HWREG(0xE000ED18U)
#define	OSEE_CORTEX_M_NVIC_SYS_PRI2_R		OSEE_HWREG(0xE000ED1CU)
#define	OSEE_CORTEX_M_NVIC_SYS_PRI3_R		OSEE_HWREG(0xE000ED20U)
#define	OSEE_CORTEX_M_NVIC_SYS_HND_CTRL_R	OSEE_HWREG(0xE000ED24U)
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_R		OSEE_HWREG(0xE000ED28U)
#define	OSEE_CORTEX_M_NVIC_HFAULT_STAT_R	OSEE_HWREG(0xE000ED2CU)
#define	OSEE_CORTEX_M_NVIC_DEBUG_STAT_R		OSEE_HWREG(0xE000ED30U)

#define	OSEE_CORTEX_M_NVIC_MM_ADDR_R		OSEE_HWREG(0xE000ED34U)
#define	OSEE_CORTEX_M_NVIC_FAULT_ADDR_R		OSEE_HWREG(0xE000ED38U)
#define	OSEE_CORTEX_M_NVIC_CPAC_R		OSEE_HWREG(0xE000ED88U)
#define	OSEE_CORTEX_M_NVIC_MPU_TYPE_R		OSEE_HWREG(0xE000ED90U)
#define	OSEE_CORTEX_M_NVIC_MPU_CTRL_R		OSEE_HWREG(0xE000ED94U)
#define	OSEE_CORTEX_M_NVIC_MPU_NUMBER_R		OSEE_HWREG(0xE000ED98U)
#define	OSEE_CORTEX_M_NVIC_MPU_BASE_R		OSEE_HWREG(0xE000ED9CU)
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR_R		OSEE_HWREG(0xE000EDA0U)
#define	OSEE_CORTEX_M_NVIC_MPU_BASE1_R		OSEE_HWREG(0xE000EDA4U)
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR1_R		OSEE_HWREG(0xE000EDA8U)
#define	OSEE_CORTEX_M_NVIC_MPU_BASE2_R		OSEE_HWREG(0xE000EDACU)
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR2_R		OSEE_HWREG(0xE000EDB0U)
#define	OSEE_CORTEX_M_NVIC_MPU_BASE3_R		OSEE_HWREG(0xE000EDB4U)
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR3_R		OSEE_HWREG(0xE000EDB8U)
#define	OSEE_CORTEX_M_NVIC_DBG_CTRL_R		OSEE_HWREG(0xE000EDF0U)
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_R		OSEE_HWREG(0xE000EDF4U)
#define	OSEE_CORTEX_M_NVIC_DBG_DATA_R		OSEE_HWREG(0xE000EDF8U)
#define	OSEE_CORTEX_M_NVIC_DBG_INT_R		OSEE_HWREG(0xE000EDFCU)
#define	OSEE_CORTEX_M_NVIC_SW_TRIG_R		OSEE_HWREG(0xE000EF00U)
#define	OSEE_CORTEX_M_NVIC_FPCC_R		OSEE_HWREG(0xE000EF34U)
#define	OSEE_CORTEX_M_NVIC_FPCA_R		OSEE_HWREG(0xE000EF38U)
#define	OSEE_CORTEX_M_NVIC_FPDSC_R		OSEE_HWREG(0xE000EF3CU)

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_INT_TYPE_R register.
 */

/* Number of interrupt lines (x32) Mask and Shift-Bits */
#define	OSEE_CORTEX_M_NVIC_INT_TYPE_LINES_M	0x0000001FU
#define	OSEE_CORTEX_M_NVIC_INT_TYPE_LINES_S	0U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_ACTLR_R register.
 */

/** Disable Out-Of-Order Floating Point */
#define	OSEE_CORTEX_M_NVIC_ACTLR_DISOOFP	0x00000200U
/** Disable CONTROL */
#define	OSEE_CORTEX_M_NVIC_ACTLR_DISFPCA	0x00000100U
/** Disable IT Folding */
#define	OSEE_CORTEX_M_NVIC_ACTLR_DISFOLD	0x00000004U
/** Disable Write Buffer */
#define	OSEE_CORTEX_M_NVIC_ACTLR_DISWBUF	0x00000002U
/** Disable Interrupts of Multiple Cycle Instructions */
#define	OSEE_CORTEX_M_NVIC_ACTLR_DISMCYC	0x00000001U

/** Interrupt Masks. */
#define	OSEE_CORTEX_M_NVIC_INT0			0x00000001U
#define	OSEE_CORTEX_M_NVIC_INT1			0x00000002U
#define	OSEE_CORTEX_M_NVIC_INT2			0x00000004U
#define	OSEE_CORTEX_M_NVIC_INT3			0x00000008U
#define	OSEE_CORTEX_M_NVIC_INT4			0x00000010U
#define	OSEE_CORTEX_M_NVIC_INT5			0x00000020U
#define	OSEE_CORTEX_M_NVIC_INT6			0x00000040U
#define	OSEE_CORTEX_M_NVIC_INT7			0x00000080U
#define	OSEE_CORTEX_M_NVIC_INT8			0x00000100U
#define	OSEE_CORTEX_M_NVIC_INT9			0x00000200U
#define	OSEE_CORTEX_M_NVIC_INT10		0x00000400U
#define	OSEE_CORTEX_M_NVIC_INT11		0x00000800U
#define	OSEE_CORTEX_M_NVIC_INT12		0x00001000U
#define	OSEE_CORTEX_M_NVIC_INT13		0x00002000U
#define	OSEE_CORTEX_M_NVIC_INT14		0x00004000U
#define	OSEE_CORTEX_M_NVIC_INT15		0x00008000U
#define	OSEE_CORTEX_M_NVIC_INT16		0x00010000U
#define	OSEE_CORTEX_M_NVIC_INT17		0x00020000U
#define	OSEE_CORTEX_M_NVIC_INT18		0x00040000U
#define	OSEE_CORTEX_M_NVIC_INT19		0x00080000U
#define	OSEE_CORTEX_M_NVIC_INT20		0x00100000U
#define	OSEE_CORTEX_M_NVIC_INT21		0x00200000U
#define	OSEE_CORTEX_M_NVIC_INT22		0x00400000U
#define	OSEE_CORTEX_M_NVIC_INT23		0x00800000U
#define	OSEE_CORTEX_M_NVIC_INT24		0x01000000U
#define	OSEE_CORTEX_M_NVIC_INT25		0x02000000U
#define	OSEE_CORTEX_M_NVIC_INT26		0x04000000U
#define	OSEE_CORTEX_M_NVIC_INT27		0x08000000U
#define	OSEE_CORTEX_M_NVIC_INT28		0x10000000U
#define	OSEE_CORTEX_M_NVIC_INT29		0x20000000U
#define	OSEE_CORTEX_M_NVIC_INT30		0x40000000U
#define	OSEE_CORTEX_M_NVIC_INT31		0x80000000U

#define	OSEE_CORTEX_M_NVIC_INT32		0x00000001U
#define	OSEE_CORTEX_M_NVIC_INT33		0x00000002U
#define	OSEE_CORTEX_M_NVIC_INT34		0x00000004U
#define	OSEE_CORTEX_M_NVIC_INT35		0x00000008U
#define	OSEE_CORTEX_M_NVIC_INT36		0x00000010U
#define	OSEE_CORTEX_M_NVIC_INT37		0x00000020U
#define	OSEE_CORTEX_M_NVIC_INT38		0x00000040U
#define	OSEE_CORTEX_M_NVIC_INT39		0x00000080U
#define	OSEE_CORTEX_M_NVIC_INT40		0x00000100U
#define	OSEE_CORTEX_M_NVIC_INT41		0x00000200U
#define	OSEE_CORTEX_M_NVIC_INT42		0x00000400U
#define	OSEE_CORTEX_M_NVIC_INT43		0x00000800U
#define	OSEE_CORTEX_M_NVIC_INT44		0x00001000U
#define	OSEE_CORTEX_M_NVIC_INT45		0x00002000U
#define	OSEE_CORTEX_M_NVIC_INT46		0x00004000U
#define	OSEE_CORTEX_M_NVIC_INT47		0x00008000U
#define	OSEE_CORTEX_M_NVIC_INT48		0x00010000U
#define	OSEE_CORTEX_M_NVIC_INT49		0x00020000U
#define	OSEE_CORTEX_M_NVIC_INT50		0x00040000U
#define	OSEE_CORTEX_M_NVIC_INT51		0x00080000U
#define	OSEE_CORTEX_M_NVIC_INT52		0x00100000U
#define	OSEE_CORTEX_M_NVIC_INT53		0x00200000U
#define	OSEE_CORTEX_M_NVIC_INT54		0x00400000U
#define	OSEE_CORTEX_M_NVIC_INT55		0x00800000U
#define	OSEE_CORTEX_M_NVIC_INT56		0x01000000U
#define	OSEE_CORTEX_M_NVIC_INT57		0x02000000U
#define	OSEE_CORTEX_M_NVIC_INT58		0x04000000U
#define	OSEE_CORTEX_M_NVIC_INT59		0x08000000U
#define	OSEE_CORTEX_M_NVIC_INT60		0x10000000U
#define	OSEE_CORTEX_M_NVIC_INT61		0x20000000U
#define	OSEE_CORTEX_M_NVIC_INT62		0x40000000U
#define	OSEE_CORTEX_M_NVIC_INT63		0x80000000U

#define	OSEE_CORTEX_M_NVIC_INT64		0x00000001U
#define	OSEE_CORTEX_M_NVIC_INT65		0x00000002U
#define	OSEE_CORTEX_M_NVIC_INT66		0x00000004U
#define	OSEE_CORTEX_M_NVIC_INT67		0x00000008U
#define	OSEE_CORTEX_M_NVIC_INT68		0x00000010U
#define	OSEE_CORTEX_M_NVIC_INT69		0x00000020U
#define	OSEE_CORTEX_M_NVIC_INT70		0x00000040U
#define	OSEE_CORTEX_M_NVIC_INT71		0x00000080U
#define	OSEE_CORTEX_M_NVIC_INT72		0x00000100U
#define	OSEE_CORTEX_M_NVIC_INT73		0x00000200U
#define	OSEE_CORTEX_M_NVIC_INT74		0x00000400U
#define	OSEE_CORTEX_M_NVIC_INT75		0x00000800U
#define	OSEE_CORTEX_M_NVIC_INT76		0x00001000U
#define	OSEE_CORTEX_M_NVIC_INT77		0x00002000U
#define	OSEE_CORTEX_M_NVIC_INT78		0x00004000U
#define	OSEE_CORTEX_M_NVIC_INT79		0x00008000U
#define	OSEE_CORTEX_M_NVIC_INT80		0x00010000U
#define	OSEE_CORTEX_M_NVIC_INT81		0x00020000U
#define	OSEE_CORTEX_M_NVIC_INT82		0x00040000U
#define	OSEE_CORTEX_M_NVIC_INT83		0x00080000U
#define	OSEE_CORTEX_M_NVIC_INT84		0x00100000U
#define	OSEE_CORTEX_M_NVIC_INT85		0x00200000U
#define	OSEE_CORTEX_M_NVIC_INT86		0x00400000U
#define	OSEE_CORTEX_M_NVIC_INT87		0x00800000U
#define	OSEE_CORTEX_M_NVIC_INT88		0x01000000U
#define	OSEE_CORTEX_M_NVIC_INT89		0x02000000U
#define	OSEE_CORTEX_M_NVIC_INT90		0x04000000U
#define	OSEE_CORTEX_M_NVIC_INT91		0x08000000U
#define	OSEE_CORTEX_M_NVIC_INT92		0x10000000U
#define	OSEE_CORTEX_M_NVIC_INT93		0x20000000U
#define	OSEE_CORTEX_M_NVIC_INT94		0x40000000U
#define	OSEE_CORTEX_M_NVIC_INT95		0x80000000U

#define	OSEE_CORTEX_M_NVIC_INT96		0x00000001U
#define	OSEE_CORTEX_M_NVIC_INT97		0x00000002U
#define	OSEE_CORTEX_M_NVIC_INT98		0x00000004U
#define	OSEE_CORTEX_M_NVIC_INT99		0x00000008U
#define	OSEE_CORTEX_M_NVIC_INT100		0x00000010U
#define	OSEE_CORTEX_M_NVIC_INT101		0x00000020U
#define	OSEE_CORTEX_M_NVIC_INT102		0x00000040U
#define	OSEE_CORTEX_M_NVIC_INT103		0x00000080U
#define	OSEE_CORTEX_M_NVIC_INT104		0x00000100U
#define	OSEE_CORTEX_M_NVIC_INT105		0x00000200U
#define	OSEE_CORTEX_M_NVIC_INT106		0x00000400U
#define	OSEE_CORTEX_M_NVIC_INT107		0x00000800U
#define	OSEE_CORTEX_M_NVIC_INT108		0x00001000U
#define	OSEE_CORTEX_M_NVIC_INT109		0x00002000U
#define	OSEE_CORTEX_M_NVIC_INT110		0x00004000U
#define	OSEE_CORTEX_M_NVIC_INT111		0x00008000U
#define	OSEE_CORTEX_M_NVIC_INT112		0x00010000U
#define	OSEE_CORTEX_M_NVIC_INT113		0x00020000U
#define	OSEE_CORTEX_M_NVIC_INT114		0x00040000U
#define	OSEE_CORTEX_M_NVIC_INT115		0x00080000U
#define	OSEE_CORTEX_M_NVIC_INT116		0x00100000U
#define	OSEE_CORTEX_M_NVIC_INT117		0x00200000U
#define	OSEE_CORTEX_M_NVIC_INT118		0x00400000U
#define	OSEE_CORTEX_M_NVIC_INT119		0x00800000U
#define	OSEE_CORTEX_M_NVIC_INT120		0x01000000U
#define	OSEE_CORTEX_M_NVIC_INT121		0x02000000U
#define	OSEE_CORTEX_M_NVIC_INT122		0x04000000U
#define	OSEE_CORTEX_M_NVIC_INT123		0x08000000U
#define	OSEE_CORTEX_M_NVIC_INT124		0x10000000U
#define	OSEE_CORTEX_M_NVIC_INT125		0x20000000U
#define	OSEE_CORTEX_M_NVIC_INT126		0x40000000U
#define	OSEE_CORTEX_M_NVIC_INT127		0x80000000U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_EN0_R register.
 */
#define	OSEE_CORTEX_M_NVIC_EN0_INT_M		0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_EN1_R register.
 */
#define	OSEE_CORTEX_M_NVIC_EN1_INT_M		0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_EN2_R register.
 */
#define	OSEE_CORTEX_M_NVIC_EN2_INT_M		0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_EN3_R register.
 */
#define	OSEE_CORTEX_M_NVIC_EN3_INT_M		0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_EN4 register.
 */
#define	OSEE_CORTEX_M_NVIC_EN4_INT_M		0x0000000FU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_DIS0_R register.
 */
#define	OSEE_CORTEX_M_NVIC_DIS0_INT_M		0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_DIS1_R register.
 */
#define	OSEE_CORTEX_M_NVIC_DIS1_INT_M		0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_DIS2_R register.
 */
#define	OSEE_CORTEX_M_NVIC_DIS2_INT_M		0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_DIS3_R register.
 */
#define	OSEE_CORTEX_M_NVIC_DIS3_INT_M		0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_DIS4_R register.
 */
#define	OSEE_CORTEX_M_NVIC_DIS4_INT_M		0x0000000FU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PEND0_R register.
 */
#define	OSEE_CORTEX_M_NVIC_PEND0_INT_M		0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PEND1_R register.
 */
#define	OSEE_CORTEX_M_NVIC_PEND1_INT_M		0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PEND2_R register.
 */
#define	OSEE_CORTEX_M_NVIC_PEND2_INT_M		0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PEND3_R register.
 */
#define	OSEE_CORTEX_M_NVIC_PEND3_INT_M		0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PEND4_R register.
 */
#define	OSEE_CORTEX_M_NVIC_PEND4_INT_M		0x0000000FU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_UNPEND0_R register.
 */
#define	OSEE_CORTEX_M_NVIC_UNPEND0_INT_M	0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_UNPEND1_R register.
 */
#define	OSEE_CORTEX_M_NVIC_UNPEND1_INT_M	0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_UNPEND2_R register.
 */
#define	OSEE_CORTEX_M_NVIC_UNPEND2_INT_M	0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_UNPEND3_R register.
 */
#define	OSEE_CORTEX_M_NVIC_UNPEND3_INT_M	0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_UNPEND4_R register.
 */
#define	OSEE_CORTEX_M_NVIC_UNPEND4_INT_M	0x0000000FU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_ACTIVE0_R register.
 */
#define	OSEE_CORTEX_M_NVIC_ACTIVE0_INT_M	0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_ACTIVE1_R register.
 */
#define	OSEE_CORTEX_M_NVIC_ACTIVE1_INT_M	0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_ACTIVE2_R register.
 */
#define	OSEE_CORTEX_M_NVIC_ACTIVE2_INT_M	0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_ACTIVE3_R register.
 */
#define	OSEE_CORTEX_M_NVIC_ACTIVE3_INT_M	0xFFFFFFFFU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_ACTIVE4_R register.
 */
#define	OSEE_CORTEX_M_NVIC_ACTIVE4_INT_M	0x0000000FU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI0_R register.
 */

/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI_INT_3_M		0xF0000000U	/* 3 */
#define	OSEE_CORTEX_M_NVIC_PRI_INT_2_M		0x00F00000U	/* 2 */
#define	OSEE_CORTEX_M_NVIC_PRI_INT_1_M		0x0000F000U	/* 1 */
#define	OSEE_CORTEX_M_NVIC_PRI_INT_0_M		0x000000F0U	/* 0 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI_INT_3_S		28U
#define	OSEE_CORTEX_M_NVIC_PRI_INT_2_S		20U
#define	OSEE_CORTEX_M_NVIC_PRI_INT_1_S		12U
#define	OSEE_CORTEX_M_NVIC_PRI_INT_0_S		4U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI0_R register.
 */

/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI0_INT3_M		0xE0000000U	/* 3 */
#define	OSEE_CORTEX_M_NVIC_PRI0_INT2_M		0x00E00000U	/* 2 */
#define	OSEE_CORTEX_M_NVIC_PRI0_INT1_M		0x0000E000U	/* 1 */
#define	OSEE_CORTEX_M_NVIC_PRI0_INT0_M		0x000000E0U	/* 0 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI0_INT3_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI0_INT2_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI0_INT1_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI0_INT0_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI1_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI1_INT7_M		0xE0000000U	/* 7 */
#define	OSEE_CORTEX_M_NVIC_PRI1_INT6_M		0x00E00000U	/* 6 */
#define	OSEE_CORTEX_M_NVIC_PRI1_INT5_M		0x0000E000U	/* 5 */
#define	OSEE_CORTEX_M_NVIC_PRI1_INT4_M		0x000000E0U	/* 4 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI1_INT7_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI1_INT6_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI1_INT5_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI1_INT4_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI2_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI2_INT11_M		0xE0000000U	/* 11 */
#define	OSEE_CORTEX_M_NVIC_PRI2_INT10_M		0x00E00000U	/* 10 */
#define	OSEE_CORTEX_M_NVIC_PRI2_INT9_M		0x0000E000U	/* 9 */
#define	OSEE_CORTEX_M_NVIC_PRI2_INT8_M		0x000000E0U	/* 8 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI2_INT11_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI2_INT10_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI2_INT9_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI2_INT8_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI3_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI3_INT15_M		0xE0000000U	/* 15 */
#define	OSEE_CORTEX_M_NVIC_PRI3_INT14_M		0x00E00000U	/* 14 */
#define	OSEE_CORTEX_M_NVIC_PRI3_INT13_M		0x0000E000U	/* 13 */
#define	OSEE_CORTEX_M_NVIC_PRI3_INT12_M		0x000000E0U	/* 12 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI3_INT15_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI3_INT14_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI3_INT13_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI3_INT12_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI4_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI4_INT19_M		0xE0000000U	/* 19 */
#define	OSEE_CORTEX_M_NVIC_PRI4_INT18_M		0x00E00000U	/* 18 */
#define	OSEE_CORTEX_M_NVIC_PRI4_INT17_M		0x0000E000U	/* 17 */
#define	OSEE_CORTEX_M_NVIC_PRI4_INT16_M		0x000000E0U	/* 16 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI4_INT19_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI4_INT18_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI4_INT17_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI4_INT16_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI5_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI5_INT23_M		0xE0000000U	/* 23 */
#define	OSEE_CORTEX_M_NVIC_PRI5_INT22_M		0x00E00000U	/* 22 */
#define	OSEE_CORTEX_M_NVIC_PRI5_INT21_M		0x0000E000U	/* 21 */
#define	OSEE_CORTEX_M_NVIC_PRI5_INT20_M		0x000000E0U	/* 20 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI5_INT23_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI5_INT22_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI5_INT21_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI5_INT20_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI6_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI6_INT27_M		0xE0000000U	/* 27 */
#define	OSEE_CORTEX_M_NVIC_PRI6_INT26_M		0x00E00000U	/* 26 */
#define	OSEE_CORTEX_M_NVIC_PRI6_INT25_M		0x0000E000U	/* 25 */
#define	OSEE_CORTEX_M_NVIC_PRI6_INT24_M		0x000000E0U	/* 24 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI6_INT27_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI6_INT26_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI6_INT25_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI6_INT24_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI7_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI7_INT31_M		0xE0000000U	/* 31 */
#define	OSEE_CORTEX_M_NVIC_PRI7_INT30_M		0x00E00000U	/* 30 */
#define	OSEE_CORTEX_M_NVIC_PRI7_INT29_M		0x0000E000U	/* 29 */
#define	OSEE_CORTEX_M_NVIC_PRI7_INT28_M		0x000000E0U	/* 28 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI7_INT31_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI7_INT30_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI7_INT29_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI7_INT28_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI8_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI8_INT35_M		0xE0000000U	/* 35 */
#define	OSEE_CORTEX_M_NVIC_PRI8_INT34_M		0x00E00000U	/* 34 */
#define	OSEE_CORTEX_M_NVIC_PRI8_INT33_M		0x0000E000U	/* 33 */
#define	OSEE_CORTEX_M_NVIC_PRI8_INT32_M		0x000000E0U	/* 32 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI8_INT35_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI8_INT34_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI8_INT33_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI8_INT32_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI9_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI9_INT39_M		0xE0000000U	/* 39 */
#define	OSEE_CORTEX_M_NVIC_PRI9_INT38_M		0x00E00000U	/* 38 */
#define	OSEE_CORTEX_M_NVIC_PRI9_INT37_M		0x0000E000U	/* 37 */
#define	OSEE_CORTEX_M_NVIC_PRI9_INT36_M		0x000000E0U	/* 36 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI9_INT39_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI9_INT38_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI9_INT37_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI9_INT36_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI10_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI10_INT43_M	0xE0000000U	/* 43 */
#define	OSEE_CORTEX_M_NVIC_PRI10_INT42_M	0x00E00000U	/* 42 */
#define	OSEE_CORTEX_M_NVIC_PRI10_INT41_M	0x0000E000U	/* 41 */
#define	OSEE_CORTEX_M_NVIC_PRI10_INT40_M	0x000000E0U	/* 40 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI10_INT43_S	29
#define	OSEE_CORTEX_M_NVIC_PRI10_INT42_S	21U
#define	OSEE_CORTEX_M_NVIC_PRI10_INT41_S	13U
#define	OSEE_CORTEX_M_NVIC_PRI10_INT40_S	5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI11_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI11_INT47_M	0xE0000000U	/* 47 */
#define	OSEE_CORTEX_M_NVIC_PRI11_INT46_M	0x00E00000U	/* 46 */
#define	OSEE_CORTEX_M_NVIC_PRI11_INT45_M	0x0000E000U	/* 45 */
#define	OSEE_CORTEX_M_NVIC_PRI11_INT44_M	0x000000E0U	/* 44 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI11_INT47_S	29
#define	OSEE_CORTEX_M_NVIC_PRI11_INT46_S	21U
#define	OSEE_CORTEX_M_NVIC_PRI11_INT45_S	13U
#define	OSEE_CORTEX_M_NVIC_PRI11_INT44_S	5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI12_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI12_INT51_M	0xE0000000U	/* 51 */
#define	OSEE_CORTEX_M_NVIC_PRI12_INT50_M	0x00E00000U	/* 50 */
#define	OSEE_CORTEX_M_NVIC_PRI12_INT49_M	0x0000E000U	/* 49 */
#define	OSEE_CORTEX_M_NVIC_PRI12_INT48_M	0x000000E0U	/* 48 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI12_INT51_S	29
#define	OSEE_CORTEX_M_NVIC_PRI12_INT50_S	21U
#define	OSEE_CORTEX_M_NVIC_PRI12_INT49_S	13U
#define	OSEE_CORTEX_M_NVIC_PRI12_INT48_S	5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI13_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI13_INT55_M	0xE0000000U	/* 55 */
#define	OSEE_CORTEX_M_NVIC_PRI13_INT54_M	0x00E00000U	/* 54 */
#define	OSEE_CORTEX_M_NVIC_PRI13_INT53_M	0x0000E000U	/* 53 */
#define	OSEE_CORTEX_M_NVIC_PRI13_INT52_M	0x000000E0U	/* 52 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI13_INT55_S	29
#define	OSEE_CORTEX_M_NVIC_PRI13_INT54_S	21U
#define	OSEE_CORTEX_M_NVIC_PRI13_INT53_S	13U
#define	OSEE_CORTEX_M_NVIC_PRI13_INT52_S	5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI14_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI14_INTD_M		0xE0000000U	/* 59 */
#define	OSEE_CORTEX_M_NVIC_PRI14_INTC_M		0x00E00000U	/* 58 */
#define	OSEE_CORTEX_M_NVIC_PRI14_INTB_M		0x0000E000U	/* 57 */
#define	OSEE_CORTEX_M_NVIC_PRI14_INTA_M		0x000000E0U	/* 56 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI14_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI14_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI14_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI14_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI15_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI15_INTD_M		0xE0000000U	/* 63 */
#define	OSEE_CORTEX_M_NVIC_PRI15_INTC_M		0x00E00000U	/* 62 */
#define	OSEE_CORTEX_M_NVIC_PRI15_INTB_M		0x0000E000U	/* 61 */
#define	OSEE_CORTEX_M_NVIC_PRI15_INTA_M		0x000000E0U	/* 60 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI15_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI15_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI15_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI15_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI16_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI16_INTD_M		0xE0000000U	/* 67 */
#define	OSEE_CORTEX_M_NVIC_PRI16_INTC_M		0x00E00000U	/* 66 */
#define	OSEE_CORTEX_M_NVIC_PRI16_INTB_M		0x0000E000U	/* 65 */
#define	OSEE_CORTEX_M_NVIC_PRI16_INTA_M		0x000000E0U	/* 64 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI16_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI16_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI16_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI16_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI17_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI17_INTD_M		0xE0000000U	/* 71 */
#define	OSEE_CORTEX_M_NVIC_PRI17_INTC_M		0x00E00000U	/* 70 */
#define	OSEE_CORTEX_M_NVIC_PRI17_INTB_M		0x0000E000U	/* 69 */
#define	OSEE_CORTEX_M_NVIC_PRI17_INTA_M		0x000000E0U	/* 68 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI17_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI17_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI17_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI17_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI18_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI18_INTD_M		0xE0000000U	/* 75 */
#define	OSEE_CORTEX_M_NVIC_PRI18_INTC_M		0x00E00000U	/* 74 */
#define	OSEE_CORTEX_M_NVIC_PRI18_INTB_M		0x0000E000U	/* 73 */
#define	OSEE_CORTEX_M_NVIC_PRI18_INTA_M		0x000000E0U	/* 72 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI18_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI18_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI18_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI18_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI19_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI19_INTD_M		0xE0000000U	/* 79 */
#define	OSEE_CORTEX_M_NVIC_PRI19_INTC_M		0x00E00000U	/* 78 */
#define	OSEE_CORTEX_M_NVIC_PRI19_INTB_M		0x0000E000U	/* 77 */
#define	OSEE_CORTEX_M_NVIC_PRI19_INTA_M		0x000000E0U	/* 76 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI19_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI19_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI19_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI19_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI20_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI20_INTD_M		0xE0000000U	/* 83 */
#define	OSEE_CORTEX_M_NVIC_PRI20_INTC_M		0x00E00000U	/* 82 */
#define	OSEE_CORTEX_M_NVIC_PRI20_INTB_M		0x0000E000U	/* 81 */
#define	OSEE_CORTEX_M_NVIC_PRI20_INTA_M		0x000000E0U	/* 80 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI20_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI20_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI20_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI20_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI21_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI21_INTD_M		0xE0000000U	/* 87 */
#define	OSEE_CORTEX_M_NVIC_PRI21_INTC_M		0x00E00000U	/* 86 */
#define	OSEE_CORTEX_M_NVIC_PRI21_INTB_M		0x0000E000U	/* 85 */
#define	OSEE_CORTEX_M_NVIC_PRI21_INTA_M		0x000000E0U	/* 84 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI21_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI21_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI21_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI21_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI22_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI22_INTD_M		0xE0000000U	/* 91 */
#define	OSEE_CORTEX_M_NVIC_PRI22_INTC_M		0x00E00000U	/* 90 */
#define	OSEE_CORTEX_M_NVIC_PRI22_INTB_M		0x0000E000U	/* 89 */
#define	OSEE_CORTEX_M_NVIC_PRI22_INTA_M		0x000000E0U	/* 88 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI22_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI22_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI22_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI22_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI23_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI23_INTD_M		0xE0000000U	/* 95 */
#define	OSEE_CORTEX_M_NVIC_PRI23_INTC_M		0x00E00000U	/* 94 */
#define	OSEE_CORTEX_M_NVIC_PRI23_INTB_M		0x0000E000U	/* 93 */
#define	OSEE_CORTEX_M_NVIC_PRI23_INTA_M		0x000000E0U	/* 92 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI23_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI23_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI23_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI23_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI24_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI24_INTD_M		0xE0000000U	/* 99 */
#define	OSEE_CORTEX_M_NVIC_PRI24_INTC_M		0x00E00000U	/* 98 */
#define	OSEE_CORTEX_M_NVIC_PRI24_INTB_M		0x0000E000U	/* 97 */
#define	OSEE_CORTEX_M_NVIC_PRI24_INTA_M		0x000000E0U	/* 96 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI24_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI24_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI24_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI24_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI25_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI25_INTD_M		0xE0000000U	/* 103 */
#define	OSEE_CORTEX_M_NVIC_PRI25_INTC_M		0x00E00000U	/* 102 */
#define	OSEE_CORTEX_M_NVIC_PRI25_INTB_M		0x0000E000U	/* 101 */
#define	OSEE_CORTEX_M_NVIC_PRI25_INTA_M		0x000000E0U	/* 100 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI25_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI25_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI25_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI25_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI26_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI26_INTD_M		0xE0000000U	/* 107 */
#define	OSEE_CORTEX_M_NVIC_PRI26_INTC_M		0x00E00000U	/* 106 */
#define	OSEE_CORTEX_M_NVIC_PRI26_INTB_M		0x0000E000U	/* 105 */
#define	OSEE_CORTEX_M_NVIC_PRI26_INTA_M		0x000000E0U	/* 104 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI26_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI26_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI26_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI26_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI27_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI27_INTD_M		0xE0000000U	/* 111 */
#define	OSEE_CORTEX_M_NVIC_PRI27_INTC_M		0x00E00000U	/* 110 */
#define	OSEE_CORTEX_M_NVIC_PRI27_INTB_M		0x0000E000U	/* 109 */
#define	OSEE_CORTEX_M_NVIC_PRI27_INTA_M		0x000000E0U	/* 108 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI27_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI27_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI27_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI27_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI28_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI28_INTD_M		0xE0000000U	/* 115 */
#define	OSEE_CORTEX_M_NVIC_PRI28_INTC_M		0x00E00000U	/* 114 */
#define	OSEE_CORTEX_M_NVIC_PRI28_INTB_M		0x0000E000U	/* 113 */
#define	OSEE_CORTEX_M_NVIC_PRI28_INTA_M		0x000000E0U	/* 112 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI28_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI28_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI28_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI28_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI29_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI29_INTD_M		0xE0000000U	/* 119 */
#define	OSEE_CORTEX_M_NVIC_PRI29_INTC_M		0x00E00000U	/* 118 */
#define	OSEE_CORTEX_M_NVIC_PRI29_INTB_M		0x0000E000U	/* 117 */
#define	OSEE_CORTEX_M_NVIC_PRI29_INTA_M		0x000000E0U	/* 116 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI29_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI29_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI29_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI29_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI30_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI30_INTD_M		0xE0000000U	/* 123 */
#define	OSEE_CORTEX_M_NVIC_PRI30_INTC_M		0x00E00000U	/* 122 */
#define	OSEE_CORTEX_M_NVIC_PRI30_INTB_M		0x0000E000U	/* 121 */
#define	OSEE_CORTEX_M_NVIC_PRI30_INTA_M		0x000000E0U	/* 120 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI30_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI30_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI30_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI30_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI31_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI31_INTD_M		0xE0000000U	/* 127 */
#define	OSEE_CORTEX_M_NVIC_PRI31_INTC_M		0x00E00000U	/* 126 */
#define	OSEE_CORTEX_M_NVIC_PRI31_INTB_M		0x0000E000U	/* 125 */
#define	OSEE_CORTEX_M_NVIC_PRI31_INTA_M		0x000000E0U	/* 124 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI31_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI31_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI31_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI31_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_PRI32_R register.
 */
/* Masks */
#define	OSEE_CORTEX_M_NVIC_PRI32_INTD_M		0xE0000000U	/* 131 */
#define	OSEE_CORTEX_M_NVIC_PRI32_INTC_M		0x00E00000U	/* 130 */
#define	OSEE_CORTEX_M_NVIC_PRI32_INTB_M		0x0000E000U	/* 129 */
#define	OSEE_CORTEX_M_NVIC_PRI32_INTA_M		0x000000E0U	/* 128 */
/* Shift Bits */
#define	OSEE_CORTEX_M_NVIC_PRI32_INTD_S		29U
#define	OSEE_CORTEX_M_NVIC_PRI32_INTC_S		21U
#define	OSEE_CORTEX_M_NVIC_PRI32_INTB_S		13U
#define	OSEE_CORTEX_M_NVIC_PRI32_INTA_S		5U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_CPUID_R register.
 */

/** Implementer Code Mask */
#define	OSEE_CORTEX_M_NVIC_CPUID_IMP_M		0xFF000000U
/** ARM Implementer Code Value */
#define	OSEE_CORTEX_M_NVIC_CPUID_IMP_ARM	0x41000000U
/** Variant Number Mask */
#define	OSEE_CORTEX_M_NVIC_CPUID_VAR_M		0x00F00000U
/** Constant Mask */
#define	OSEE_CORTEX_M_NVIC_CPUID_CON_M		0x000F0000U
/** Part Number Mask */
#define	OSEE_CORTEX_M_NVIC_CPUID_PARTNO_M	0x0000FFF0U
/** Cortex-M4 processor value */
#define	OSEE_CORTEX_M_NVIC_CPUID_PARTNO_CM4	0x0000C240U
/** Revision Number Mask */
#define	OSEE_CORTEX_M_NVIC_CPUID_REV_M		0x0000000FU

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_INT_CTRL_R register.
 */
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_NMI_SET		0x80000000U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_PEND_SV		0x10000000U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_UNPEND_SV		0x08000000U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_PENDSTSET		0x04000000U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_PENDSTCLR		0x02000000U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_ISR_PRE		0x00800000U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_ISR_PEND		0x00400000U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_VEC_PEN_M		0x000FF000U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_VEC_PEN_NMI		0x00002000U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_VEC_PEN_HARD	0x00003000U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_VEC_PEN_MEM		0x00004000U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_VEC_PEN_BUS		0x00005000U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_VEC_PEN_USG		0x00006000U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_VEC_PEN_SVC		0x0000B000U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_VEC_PEN_PNDSV	0x0000E000U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_VEC_PEN_TICK	0x0000F000U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_RET_BASE		0x00000800U
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_VEC_ACT_M		0x000000FFU
#define	OSEE_CORTEX_M_NVIC_INT_CTRL_VEC_ACT_S		0U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_VTABLE_R register.
 */
#define	OSEE_CORTEX_M_NVIC_VTABLE_BASE		0x20000000U // Vector Table Base
#define	OSEE_CORTEX_M_NVIC_VTABLE_OFFSET_M	0x1FFFFC00U // Vector Table Offset
#define	OSEE_CORTEX_M_NVIC_VTABLE_OFFSET_S	10

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_APINT_R register.
 */
#define	OSEE_CORTEX_M_NVIC_APINT_VECTKEY_M	0xFFFF0000U // Register Key
#define	OSEE_CORTEX_M_NVIC_APINT_VECTKEY	0x05FA0000U // Vector key
#define	OSEE_CORTEX_M_NVIC_APINT_ENDIANESS	0x00008000U // Data Endianess
#define	OSEE_CORTEX_M_NVIC_APINT_PRIGROUP_M	0x00000700U // Priority Grouping
#define	OSEE_CORTEX_M_NVIC_APINT_PRIGROUP_7_1	0x00000000U // Priority group 7.1 split
#define	OSEE_CORTEX_M_NVIC_APINT_PRIGROUP_6_2	0x00000100U // Priority group 6.2 split
#define	OSEE_CORTEX_M_NVIC_APINT_PRIGROUP_5_3	0x00000200U // Priority group 5.3 split
#define	OSEE_CORTEX_M_NVIC_APINT_PRIGROUP_4_4	0x00000300U // Priority group 4.4 split
#define	OSEE_CORTEX_M_NVIC_APINT_PRIGROUP_3_5	0x00000400U // Priority group 3.5 split
#define	OSEE_CORTEX_M_NVIC_APINT_PRIGROUP_2_6	0x00000500U // Priority group 2.6 split
#define	OSEE_CORTEX_M_NVIC_APINT_PRIGROUP_1_7	0x00000600U // Priority group 1.7 split
#define	OSEE_CORTEX_M_NVIC_APINT_PRIGROUP_0_8	0x00000700U // Priority group 0.8 split
#define	OSEE_CORTEX_M_NVIC_APINT_SYSRESETREQ 	0x00000004U // System Reset Request
#define	OSEE_CORTEX_M_NVIC_APINT_VECT_CLR_ACT	0x00000002U // Clear Active NMI / Fault
#define	OSEE_CORTEX_M_NVIC_APINT_VECT_RESET  	0x00000001U // System Reset

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_SYS_CTRL_R register.
 */
#define	OSEE_CORTEX_M_NVIC_SYS_CTRL_SEVONPEND	0x00000010U // Wake Up on Pending
#define	OSEE_CORTEX_M_NVIC_SYS_CTRL_SLEEPDEEP	0x00000004U // Deep Sleep Enable
#define	OSEE_CORTEX_M_NVIC_SYS_CTRL_SLEEPEXIT	0x00000002U // Sleep on ISR Exit

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_CFG_CTRL_R register.
 */
#define	OSEE_CORTEX_M_NVIC_CFG_CTRL_STKALIGN 	0x00000200U // Stack Alignment on Exception Entry
#define	OSEE_CORTEX_M_NVIC_CFG_CTRL_BFHFNMIGN	0x00000100U // Ignore Bus Fault in NMI and Fault
#define	OSEE_CORTEX_M_NVIC_CFG_CTRL_DIV0	0x00000010U // Trap on Divide by 0
#define	OSEE_CORTEX_M_NVIC_CFG_CTRL_UNALIGNED	0x00000008U // Trap on Unaligned Access
#define	OSEE_CORTEX_M_NVIC_CFG_CTRL_MAIN_PEND	0x00000002U // Allow Main Interrupt Trigger
#define	OSEE_CORTEX_M_NVIC_CFG_CTRL_BASE_THR 	0x00000001U // Thread State Control

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_SYS_PRI1_R register.
 */
#define	OSEE_CORTEX_M_NVIC_SYS_PRI1_USAGE_M	0x00F00000U // Usage Fault Priority
#define	OSEE_CORTEX_M_NVIC_SYS_PRI1_BUS_M	0x0000F000U // Bus Fault Priority
#define	OSEE_CORTEX_M_NVIC_SYS_PRI1_MEM_M	0x000000F0U // Memory Management Fault Priority
#define	OSEE_CORTEX_M_NVIC_SYS_PRI1_USAGE_S	20U
#define	OSEE_CORTEX_M_NVIC_SYS_PRI1_BUS_S	12U
#define	OSEE_CORTEX_M_NVIC_SYS_PRI1_MEM_S	4U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_SYS_PRI2_R register.
 */
#define	OSEE_CORTEX_M_NVIC_SYS_PRI2_SVC_M	0xF0000000U // SVCall Priority
#define	OSEE_CORTEX_M_NVIC_SYS_PRI2_SVC_S	28U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_SYS_PRI3_R register.
 */
#define	OSEE_CORTEX_M_NVIC_SYS_PRI3_TICK_M	0xF0000000U // SysTick Exception Priority
#define	OSEE_CORTEX_M_NVIC_SYS_PRI3_PENDSV_M	0x00F00000U // PendSV Priority
#define	OSEE_CORTEX_M_NVIC_SYS_PRI3_DEBUG_M	0x000000F0U // Debug Priority
#define	OSEE_CORTEX_M_NVIC_SYS_PRI3_TICK_S	28U
#define	OSEE_CORTEX_M_NVIC_SYS_PRI3_PENDSV_S	20U
#define	OSEE_CORTEX_M_NVIC_SYS_PRI3_DEBUG_S	4U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_SYS_HND_CTRL_R register.
 */
#define	OSEE_CORTEX_M_NVIC_SYS_HND_CTRL_USAGE	0x00040000U // Usage Fault Enable
#define	OSEE_CORTEX_M_NVIC_SYS_HND_CTRL_BUS	0x00020000U // Bus Fault Enable
#define	OSEE_CORTEX_M_NVIC_SYS_HND_CTRL_MEM	0x00010000U // Memory Management Fault Enable
#define	OSEE_CORTEX_M_NVIC_SYS_HND_CTRL_SVC	0x00008000U // SVC Call Pending
#define	OSEE_CORTEX_M_NVIC_SYS_HND_CTRL_BUSP	0x00004000U // Bus Fault Pending
#define	OSEE_CORTEX_M_NVIC_SYS_HND_CTRL_MEMP	0x00002000U // Memory Management Fault Pending
#define	OSEE_CORTEX_M_NVIC_SYS_HND_CTRL_USAGEP	0x00001000U // Usage Fault Pending
#define	OSEE_CORTEX_M_NVIC_SYS_HND_CTRL_TICK	0x00000800U // SysTick Exception Active
#define	OSEE_CORTEX_M_NVIC_SYS_HND_CTRL_PNDSV	0x00000400U // PendSV Exception Active
#define	OSEE_CORTEX_M_NVIC_SYS_HND_CTRL_MON	0x00000100U // Debug Monitor Active
#define	OSEE_CORTEX_M_NVIC_SYS_HND_CTRL_SVCA	0x00000080U // SVC Call Active
#define	OSEE_CORTEX_M_NVIC_SYS_HND_CTRL_USGA	0x00000008U // Usage Fault Active
#define	OSEE_CORTEX_M_NVIC_SYS_HND_CTRL_BUSA	0x00000002U // Bus Fault Active
#define	OSEE_CORTEX_M_NVIC_SYS_HND_CTRL_MEMA	0x00000001U // Memory Management Fault Active

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_FAULT_STAT_R register.
 */
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_DIV0	0x02000000U // Divide-by-Zero Usage Fault
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_UNALIGN	0x01000000U // Unaligned Access Usage Fault
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_NOCP	0x00080000U // No Coprocessor Usage Fault
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_INVPC	0x00040000U // Invalid PC Load Usage Fault
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_INVSTAT	0x00020000U // Invalid State Usage Fault
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_UNDEF	0x00010000U // Undefined Instruction Usage Fault
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_BFARV	0x00008000U // Bus Fault Address Register Valid
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_BLSPERR	0x00002000U // Bus Fault on Floating-Point Lazy State Preservation
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_BSTKE	0x00001000U // Stack Bus Fault
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_BUSTKE	0x00000800U // Unstack Bus Fault
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_IMPRE	0x00000400U // Imprecise Data Bus Error
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_PRECISE	0x00000200U // Precise Data Bus Error
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_IBUS	0x00000100U // Instruction Bus Error
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_MMARV	0x00000080U // Memory Management Fault Address Register Valid
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_MLSPERR	0x00000020U // Memory Management Fault on Floating-Point Lazy State Preservation
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_MSTKE	0x00000010U // Stack Access Violation
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_MUSTKE	0x00000008U // Unstack Access Violation
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_DERR	0x00000002U // Data Access Violation
#define	OSEE_CORTEX_M_NVIC_FAULT_STAT_IERR	0x00000001U // Instruction Access Violation

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_HFAULT_STAT_R register.
 */
#define	OSEE_CORTEX_M_NVIC_HFAULT_STAT_DBG	0x80000000U // Debug Event
#define	OSEE_CORTEX_M_NVIC_HFAULT_STAT_FORCED	0x40000000U // Forced Hard Fault
#define	OSEE_CORTEX_M_NVIC_HFAULT_STAT_VECT	0x00000002U // Vector Table Read Fault

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_DEBUG_STAT_R register.
 */
#define	OSEE_CORTEX_M_NVIC_DEBUG_STAT_EXTRNL	0x00000010U // EDBGRQ asserted
#define	OSEE_CORTEX_M_NVIC_DEBUG_STAT_VCATCH	0x00000008U // Vector catch
#define	OSEE_CORTEX_M_NVIC_DEBUG_STAT_DWTTRAP	0x00000004U // DWT match
#define	OSEE_CORTEX_M_NVIC_DEBUG_STAT_BKPT	0x00000002U // Breakpoint instruction
#define	OSEE_CORTEX_M_NVIC_DEBUG_STAT_HALTED	0x00000001U // Halt request

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_MM_ADDR_R register.
 */
#define	OSEE_CORTEX_M_NVIC_MM_ADDR_M		0xFFFFFFFFU // Fault Address
#define	OSEE_CORTEX_M_NVIC_MM_ADDR_S		0U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_FAULT_ADDR
 *_R register.
 */
#define	OSEE_CORTEX_M_NVIC_FAULT_ADDR_M		0xFFFFFFFFU // Fault Address
#define	OSEE_CORTEX_M_NVIC_FAULT_ADDR_S		0U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_CPAC_R register.
 */
#define	OSEE_CORTEX_M_NVIC_CPAC_CP11_M		0x00C00000U // CP11 Coprocessor Access Privilege
#define	OSEE_CORTEX_M_NVIC_CPAC_CP11_DIS	0x00000000U // Access Denied
#define	OSEE_CORTEX_M_NVIC_CPAC_CP11_PRIV	0x00400000U // Privileged Access Only
#define	OSEE_CORTEX_M_NVIC_CPAC_CP11_FULL	0x00C00000U // Full Access
#define	OSEE_CORTEX_M_NVIC_CPAC_CP10_M		0x00300000U // CP10 Coprocessor Access Privilege
#define	OSEE_CORTEX_M_NVIC_CPAC_CP10_DIS	0x00000000U // Access Denied
#define	OSEE_CORTEX_M_NVIC_CPAC_CP10_PRIV	0x00100000U // Privileged Access Only
#define	OSEE_CORTEX_M_NVIC_CPAC_CP10_FULL	0x00300000U // Full Access

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_MPU_TYPE_R register.
 */
#define	OSEE_CORTEX_M_NVIC_MPU_TYPE_IREGION_M	0x00FF0000U // Number of I Regions
#define	OSEE_CORTEX_M_NVIC_MPU_TYPE_DREGION_M	0x0000FF00U // Number of D Regions
#define	OSEE_CORTEX_M_NVIC_MPU_TYPE_SEPARATE 	0x00000001U // Separate or Unified MPU
#define	OSEE_CORTEX_M_NVIC_MPU_TYPE_IREGION_S	16U
#define	OSEE_CORTEX_M_NVIC_MPU_TYPE_DREGION_S	8U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_MPU_CTRL_R register.
 */
#define	OSEE_CORTEX_M_NVIC_MPU_CTRL_PRIVDEFEN	0x00000004U // MPU Default Region
#define	OSEE_CORTEX_M_NVIC_MPU_CTRL_HFNMIENA 	0x00000002U // MPU Enabled During Faults
#define	OSEE_CORTEX_M_NVIC_MPU_CTRL_ENABLE	0x00000001U // MPU Enable

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_MPU_NUMBER
 *_R register.
 */
#define	OSEE_CORTEX_M_NVIC_MPU_NUMBER_M		0x00000007U // MPU Region to Access
#define	OSEE_CORTEX_M_NVIC_MPU_NUMBER_S		0U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_MPU_BASE_R register.
 */
#define	OSEE_CORTEX_M_NVIC_MPU_BASE_ADDR_M	0xFFFFFFE0U // Base Address Mask
#define	OSEE_CORTEX_M_NVIC_MPU_BASE_VALID	0x00000010U // Region Number Valid
#define	OSEE_CORTEX_M_NVIC_MPU_BASE_REGION_M	0x00000007U // Region Number
#define	OSEE_CORTEX_M_NVIC_MPU_BASE_ADDR_S	5U
#define	OSEE_CORTEX_M_NVIC_MPU_BASE_REGION_S	0U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_MPU_ATTR_R register.
 */
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR_XN		0x10000000U // Instruction Access Disable
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR_AP_M	0x07000000U // Access Privilege
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR_TEX_M	0x00380000U // Type Extension Mask
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR_SHAREABLE	0x00040000U // Shareable
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR_CACHEABLE	0x00020000U // Cacheable
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR_BUFFRABLE	0x00010000U // Bufferable
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR_SRD_M	0x0000FF00U // Subregion Disable Bits
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR_SIZE_M	0x0000003EU // Region Size Mask
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR_ENABLE	0x00000001U // Region Enable

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_MPU_BASE1_R register.
 */
#define	OSEE_CORTEX_M_NVIC_MPU_BASE1_ADDR_M	0xFFFFFFE0U // Base Address Mask
#define	OSEE_CORTEX_M_NVIC_MPU_BASE1_VALID	0x00000010U // Region Number Valid
#define	OSEE_CORTEX_M_NVIC_MPU_BASE1_REGION_M	0x00000007U // Region Number
#define	OSEE_CORTEX_M_NVIC_MPU_BASE1_ADDR_S	5U
#define	OSEE_CORTEX_M_NVIC_MPU_BASE1_REGION_S	0U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_MPU_ATTR1_R register.
 */
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR1_XN		0x10000000U // Instruction Access Disable
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR1_AP_M	0x07000000U // Access Privilege
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR1_TEX_M	0x00380000U // Type Extension Mask
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR1_SHAREABLE	0x00040000U // Shareable
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR1_CACHEABLE	0x00020000U // Cacheable
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR1_BUFFRABLE	0x00010000U // Bufferable
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR1_SRD_M	0x0000FF00U // Subregion Disable Bits
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR1_SIZE_M	0x0000003EU // Region Size Mask
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR1_ENABLE	0x00000001U // Region Enable

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_MPU_BASE2_R register.
 */
#define	OSEE_CORTEX_M_NVIC_MPU_BASE2_ADDR_M	0xFFFFFFE0U // Base Address Mask
#define	OSEE_CORTEX_M_NVIC_MPU_BASE2_VALID	0x00000010U // Region Number Valid
#define	OSEE_CORTEX_M_NVIC_MPU_BASE2_REGION_M	0x00000007U // Region Number
#define	OSEE_CORTEX_M_NVIC_MPU_BASE2_ADDR_S	5U
#define	OSEE_CORTEX_M_NVIC_MPU_BASE2_REGION_S	0U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_MPU_ATTR2_R register.
 */
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR2_XN		0x10000000U // Instruction Access Disable
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR2_AP_M	0x07000000U // Access Privilege
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR2_TEX_M	0x00380000U // Type Extension Mask
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR2_SHAREABLE	0x00040000U // Shareable
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR2_CACHEABLE	0x00020000U // Cacheable
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR2_BUFFRABLE	0x00010000U // Bufferable
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR2_SRD_M	0x0000FF00U // Subregion Disable Bits
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR2_SIZE_M	0x0000003EU // Region Size Mask
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR2_ENABLE	0x00000001U // Region Enable

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_MPU_BASE3_R register.
 */
#define	OSEE_CORTEX_M_NVIC_MPU_BASE3_ADDR_M	0xFFFFFFE0U // Base Address Mask
#define	OSEE_CORTEX_M_NVIC_MPU_BASE3_VALID	0x00000010U // Region Number Valid
#define	OSEE_CORTEX_M_NVIC_MPU_BASE3_REGION_M	0x00000007U // Region Number
#define	OSEE_CORTEX_M_NVIC_MPU_BASE3_ADDR_S	5U
#define	OSEE_CORTEX_M_NVIC_MPU_BASE3_REGION_S	0U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_MPU_ATTR3_R register.
 */
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR3_XN		0x10000000U // Instruction Access Disable
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR3_AP_M	0x07000000U // Access Privilege
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR3_TEX_M	0x00380000U // Type Extension Mask
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR3_SHAREABLE	0x00040000U // Shareable
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR3_CACHEABLE	0x00020000U // Cacheable
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR3_BUFFRABLE	0x00010000U // Bufferable
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR3_SRD_M	0x0000FF00U // Subregion Disable Bits
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR3_SIZE_M	0x0000003EU // Region Size Mask
#define	OSEE_CORTEX_M_NVIC_MPU_ATTR3_ENABLE	0x00000001U // Region Enable

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_DBG_CTRL_R register.
 */
#define	OSEE_CORTEX_M_NVIC_DBG_CTRL_DBGKEY_M	0xFFFF0000U // Debug key mask
#define	OSEE_CORTEX_M_NVIC_DBG_CTRL_DBGKEY	0xA05F0000U // Debug key
#define	OSEE_CORTEX_M_NVIC_DBG_CTRL_S_RESET_ST	0x02000000U // Core has reset since last read
#define	OSEE_CORTEX_M_NVIC_DBG_CTRL_S_RETIRE_ST	0x01000000U // Core has executed insruction since last read
#define	OSEE_CORTEX_M_NVIC_DBG_CTRL_S_LOCKUP	0x00080000U // Core is locked up
#define	OSEE_CORTEX_M_NVIC_DBG_CTRL_S_SLEEP	0x00040000U // Core is sleeping
#define	OSEE_CORTEX_M_NVIC_DBG_CTRL_S_HALT	0x00020000U // Core status on halt
#define	OSEE_CORTEX_M_NVIC_DBG_CTRL_S_REGRDY	0x00010000U // Register read/write available
#define	OSEE_CORTEX_M_NVIC_DBG_CTRL_C_SNAPSTALL	0x00000020U // Breaks a stalled load/store
#define	OSEE_CORTEX_M_NVIC_DBG_CTRL_C_MASKINT	0x00000008U // Mask interrupts when stepping
#define	OSEE_CORTEX_M_NVIC_DBG_CTRL_C_STEP	0x00000004U // Step the core
#define	OSEE_CORTEX_M_NVIC_DBG_CTRL_C_HALT	0x00000002U // Halt the core
#define	OSEE_CORTEX_M_NVIC_DBG_CTRL_C_DEBUGEN	0x00000001U // Enable debug

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_DBG_XFER_R register.
 */
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_WNR	0x00010000U // Write or not read
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_SEL_M	0x0000001FU // Register
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_R0	0x00000000U // Register R0
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_R1	0x00000001U // Register R1
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_R2	0x00000002U // Register R2
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_R3	0x00000003U // Register R3
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_R4	0x00000004U // Register R4
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_R5	0x00000005U // Register R5
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_R6	0x00000006U // Register R6
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_R7	0x00000007U // Register R7
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_R8	0x00000008U // Register R8
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_R9	0x00000009U // Register R9
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_R10	0x0000000AU // Register R10
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_R11	0x0000000BU // Register R11
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_R12	0x0000000CU // Register R12
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_R13	0x0000000DU // Register R13
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_R14	0x0000000EU // Register R14
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_R15	0x0000000FU // Register R15
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_FLAGS	0x00000010U // xPSR/Flags register
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_MSP	0x00000011U // Main SP
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_PSP	0x00000012U // Process SP
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_DSP	0x00000013U // Deep SP
#define	OSEE_CORTEX_M_NVIC_DBG_XFER_REG_CFBP	0x00000014U // Control/Fault/BasePri/PriMask

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_DBG_DATA_R register.
 */
#define	OSEE_CORTEX_M_NVIC_DBG_DATA_M		0xFFFFFFFFU // Data temporary cache
#define	OSEE_CORTEX_M_NVIC_DBG_DATA_S		0U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_DBG_INT_R register.
 */
#define	OSEE_CORTEX_M_NVIC_DBG_INT_HARDERR	0x00000400U // Debug trap on hard fault
#define	OSEE_CORTEX_M_NVIC_DBG_INT_INTERR	0x00000200U // Debug trap on interrupt errors
#define	OSEE_CORTEX_M_NVIC_DBG_INT_BUSERR	0x00000100U // Debug trap on bus error
#define	OSEE_CORTEX_M_NVIC_DBG_INT_STATERR	0x00000080U // Debug trap on usage fault state
#define	OSEE_CORTEX_M_NVIC_DBG_INT_CHKERR	0x00000040U // Debug trap on usage fault check
#define	OSEE_CORTEX_M_NVIC_DBG_INT_NOCPERR	0x00000020U // Debug trap on coprocessor error
#define	OSEE_CORTEX_M_NVIC_DBG_INT_MMERR	0x00000010U // Debug trap on mem manage fault
#define	OSEE_CORTEX_M_NVIC_DBG_INT_RESET	0x00000008U // Core reset status
#define	OSEE_CORTEX_M_NVIC_DBG_INT_RSTPENDCLR	0x00000004U // Clear pending core reset
#define	OSEE_CORTEX_M_NVIC_DBG_INT_RSTPENDING	0x00000002U // Core reset is pending
#define	OSEE_CORTEX_M_NVIC_DBG_INT_RSTVCATCH	0x00000001U // Reset vector catch

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_SW_TRIG_R register.
 */
#define	OSEE_CORTEX_M_NVIC_SW_TRIG_INTID_M	0x000000FFU /* ID */
#define	OSEE_CORTEX_M_NVIC_SW_TRIG_INTID_S	0U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_FPCC_R register.
 */
#define	OSEE_CORTEX_M_NVIC_FPCC_ASPEN		0x80000000U // Automatic State Preservation Enable
#define	OSEE_CORTEX_M_NVIC_FPCC_LSPEN		0x40000000U // Lazy State Preservation Enable
#define	OSEE_CORTEX_M_NVIC_FPCC_MONRDY		0x00000100U // Monitor Ready
#define	OSEE_CORTEX_M_NVIC_FPCC_BFRDY		0x00000040U // Bus Fault Ready
#define	OSEE_CORTEX_M_NVIC_FPCC_MMRDY		0x00000020U // Memory Management Fault Ready
#define	OSEE_CORTEX_M_NVIC_FPCC_HFRDY		0x00000010U // Hard Fault Ready
#define	OSEE_CORTEX_M_NVIC_FPCC_THREAD		0x00000008U // Thread Mode
#define	OSEE_CORTEX_M_NVIC_FPCC_USER		0x00000002U // User Privilege Level
#define	OSEE_CORTEX_M_NVIC_FPCC_LSPACT		0x00000001U // Lazy State Preservation Active

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_FPCA_R register.
 */
#define	OSEE_CORTEX_M_NVIC_FPCA_ADDRESS_M	0xFFFFFFF8U // Address
#define	OSEE_CORTEX_M_NVIC_FPCA_ADDRESS_S	3U

/*
 * The following are defines for the bit fields in the
 * OSEE_CORTEX_M_NVIC_FPDSC_R register.
 */
#define	OSEE_CORTEX_M_NVIC_FPDSC_AHP		0x04000000U // AHP Bit Default
#define	OSEE_CORTEX_M_NVIC_FPDSC_DN		0x02000000U // DN Bit Default
#define	OSEE_CORTEX_M_NVIC_FPDSC_FZ		0x01000000U // FZ Bit Default
#define	OSEE_CORTEX_M_NVIC_FPDSC_RMODE_M	0x00C00000U // RMODE Bit Default
#define	OSEE_CORTEX_M_NVIC_FPDSC_RMODE_RN	0x00000000U // Round to Nearest (RN) mode
#define	OSEE_CORTEX_M_NVIC_FPDSC_RMODE_RP	0x00400000U // Round towards Plus Infinity (RP) mode
#define	OSEE_CORTEX_M_NVIC_FPDSC_RMODE_RM	0x00800000U // Round towards Minus Infinity (RM) mode
#define	OSEE_CORTEX_M_NVIC_FPDSC_RMODE_RZ	0x00C00000U // Round towards Zero (RZ) mode

/* Register Shift-Bits Number */
#define	OSEE_CORTEX_M_NVIC_REG_S	2U

/* NVIC Interrupt Registers Base Address */
#define	OSEE_CORTEX_M_NVIC_INT_REG_B		(OsEE_reg)0xE000E100U

/* NVIC Interrupt Register Mask */
#define	OSEE_CORTEX_M_NVIC_INT_REG_M		(OsEE_reg)0x0000001FU

/* NVIC Interrupt Register Shift-Bits Number */
#define	OSEE_CORTEX_M_NVIC_INT_REG_S		(OsEE_reg)0x00000005U

/* NVIC Interrupt Register Number */
#define	OSEE_CORTEX_M_NVIC_INT_REG_N(_int)	(			\
		( (OsEE_reg)(_int) >> OSEE_CORTEX_M_NVIC_INT_REG_S) <<	\
		OSEE_CORTEX_M_NVIC_REG_S				\
	)

/* NVIC Interrupt Register */
#define	OSEE_CORTEX_M_NVIC_INT_REG(_int,_base)	OSEE_HWREG(		\
		(_base) + OSEE_CORTEX_M_NVIC_INT_REG_N(_int)		\
	)

/* NVIC Interrupt Mask */
#define	OSEE_CORTEX_M_NVIC_INT_M(_int)		(			\
		(OsEE_reg)0x00000001U << (				\
			(OsEE_reg)(_int) & OSEE_CORTEX_M_NVIC_INT_REG_M	\
		)							\
	)

/* NVIC Interrupt Priority Registers Base Address */
#define	OSEE_CORTEX_M_NVIC_INT_PRI_REG_B	(OsEE_reg)0xE000E400U

/* NVIC Interrupt Priority Register Mask */
#define	OSEE_CORTEX_M_NVIC_INT_PRI_REG_M	(OsEE_reg)0x00000003U

/* NVIC Interrupt Priority Register Shift-Bits Number */
#define	OSEE_CORTEX_M_NVIC_INT_PRI_REG_S	(OsEE_reg)0x00000002U

/* NVIC Interrupt Priority Register Number */
#define	OSEE_CORTEX_M_NVIC_INT_PRI_REG_N(_int)	(			\
		(							\
			(OsEE_reg)(_int) >>				\
			OSEE_CORTEX_M_NVIC_INT_PRI_REG_S		\
		) << OSEE_CORTEX_M_NVIC_REG_S				\
	)

/* NVIC Interrupt Priority Register */
#define	OSEE_CORTEX_M_NVIC_INT_PRI_REG(_int)	OSEE_HWREG(		\
		OSEE_CORTEX_M_NVIC_INT_PRI_REG_B +			\
		OSEE_CORTEX_M_NVIC_INT_PRI_REG_N(_int)			\
	)

/* NVIC Interrupt Priority Mask */
#define	OSEE_CORTEX_M_NVIC_INT_PRI_M(_int)	(			\
		(OsEE_reg)0x000000F0U << (				\
			(						\
				(OsEE_reg)(_int) &			\
				OSEE_CORTEX_M_NVIC_INT_PRI_REG_M	\
			) << OSEE_CORTEX_M_NVIC_INT_PRI_REG_M		\
		)							\
	)

/* NVIC Interrupt Priority Shift-Bits Number */
#define	OSEE_CORTEX_M_NVIC_INT_PRI_S		(OsEE_reg)0x00000004U

/* NVIC Interrupt Priority */
#define	OSEE_CORTEX_M_NVIC_INT_PRI(_int,_pri)	(			\
		(							\
			(OsEE_reg)(_pri) <<				\
			OSEE_CORTEX_M_NVIC_INT_PRI_S			\
		) << (							\
			(						\
				(OsEE_reg)(_int) &			\
				OSEE_CORTEX_M_NVIC_INT_PRI_REG_M	\
			) << OSEE_CORTEX_M_NVIC_INT_PRI_REG_M		\
		)							\
	)

/* NVIC Interrupt Set Pending Registers Base Address */
#define	OSEE_CORTEX_M_NVIC_INT_SET_PENDING_REG_B	(OsEE_reg)0xE000E200U

/* NVIC Interrupt Clear Pending Registers Base Address */
#define	OSEE_CORTEX_M_NVIC_INT_CLR_PENDING_REG_B	(OsEE_reg)0xE000E280U

/* NVIC Enable Interrupt */
#define	OSEE_CORTEX_M_NVIC_INT_ENABLE(_int)	(			\
		OSEE_CORTEX_M_NVIC_INT_REG(				\
			(_int), OSEE_CORTEX_M_NVIC_INT_REG_B		\
		) |= OSEE_CORTEX_M_NVIC_INT_M(_int)			\
	)

/* NVIC Disable Interrupt */
#define	OSEE_CORTEX_M_NVIC_INT_DISABLE(_int)	(			\
		OSEE_CORTEX_M_NVIC_INT_REG(				\
			(_int), OSEE_CORTEX_M_NVIC_INT_REG_B		\
		) &= ~OSEE_CORTEX_M_NVIC_INT_M(_int)			\
	)

/* NVIC Clear Priority */
#define	OSEE_CORTEX_M_NVIC_CLR_PRI(_int)	(			\
		OSEE_CORTEX_M_NVIC_INT_PRI_REG(_int) &=			\
		~OSEE_CORTEX_M_NVIC_INT_PRI_M(_int)			\
	)

/* NVIC Set Priority */
#define	OSEE_CORTEX_M_NVIC_SET_PRI(_int,_pri)	{			\
		OSEE_CORTEX_M_NVIC_CLR_PRI(_int);			\
		(							\
			OSEE_CORTEX_M_NVIC_INT_PRI_REG(_int) |= (	\
				OSEE_CORTEX_M_NVIC_INT_PRI_M(_int) &	\
				OSEE_CORTEX_M_NVIC_INT_PRI(_int, _pri)	\
			)						\
		);							\
	}

/* NVIC Get Priority */
#define	OSEE_CORTEX_M_NVIC_GET_PRI(_int)	(			\
		(							\
			(						\
				OSEE_CORTEX_M_NVIC_INT_PRI_REG(_int) &	\
				OSEE_CORTEX_M_NVIC_INT_PRI_M(_int)	\
			) >> (						\
				(					\
					(OsEE_reg)(_int) &		\
				OSEE_CORTEX_M_NVIC_INT_PRI_REG_M	\
				) << OSEE_CORTEX_M_NVIC_INT_PRI_REG_M	\
			)						\
		) >> OSEE_CORTEX_M_NVIC_INT_PRI_S			\
	)

/* NVIC Set Pending Interrupt */
#define	OSEE_CORTEX_M_NVIC_INT_SET_PENDING(_int)	(		\
		OSEE_CORTEX_M_NVIC_INT_REG(				\
			(_int),						\
			OSEE_CORTEX_M_NVIC_INT_SET_PENDING_REG_B	\
		) |= OSEE_CORTEX_M_NVIC_INT_M(_int)			\
	)

/* NVIC Clear Pending Interrupt */
#define	OSEE_CORTEX_M_NVIC_INT_CLR_PENDING(_int)	(		\
		OSEE_CORTEX_M_NVIC_INT_REG(				\
			(_int),						\
			OSEE_CORTEX_M_NVIC_INT_CLR_PENDING_REG_B	\
		) |= OSEE_CORTEX_M_NVIC_INT_M(_int)			\
	)

#if (defined(__cplusplus))
}
#endif

#endif	/* OSEE_CORTEX_M_NVIC_H */
